1. Field of the Invention
The present invention relates to a removing method of a hard mask, and particularly to a removing method of a hard mask applied in a fabricating process of a semiconductor device.
2. Description of the Related Art
In the technology for manufacturing an integrated circuit, a gate structure including an insulating layer with high dielectric constant (high-K) and a metal gate (hereafter called HK/MG for short) has been widely used. Such gate structure can reduce a current leakage, thereby improving the performance of the integrated circuit. Currently, the HK/MG can be selectively fabricated by two processes including a gate-first process and a gate-last process. In the gate-first process, the HK/MG is previously disposed before forming the gate structure. In the gate-last process, after a poly-silicon dummy gate is removed, the metal gate of the HK/MG is filled
FIGS. 1(a)-1(b) illustrate a partial process flow of a conventional method for fabricating a partial integrated circuit of two metal-oxide-semiconductor field-effect transistors (MOSFETs) 101, 102. Referring to FIG. 1(a), at first, a number of shallow trench isolations (STI) 109 are defined in a substrate 10. Each of the shallow trench isolations 109 is configured for isolating two neighboring MOSFETs, for example, the two MOSFETs 101, 102, formed on the substrate 10. A gate 11 of each of the MOSFETs 101, 102 covered by a hard mask 16 is formed on a gate insulating layer 12 on the substrate 10. If the gate-first process is applied, the gate 11 is comprised of a poly-silicon gate 110, a work function metal gate 111 and a capping layer 112 (see FIG. 3(a)). If the gate-last process is applied, the gate 11 is comprised of a poly-silicon dummy gate 113 and a barrier metal 114 (see FIG. 3(b)). The gate 11 is surrounded by a spacer 13. The gate insulating layer 12 can be a multiplayer structure as shown in FIG. 1(a), which includes a silicon oxide layer 120 and a high-K insulating layer 121. The spacer 13 also can be a multilayer structure shown in FIG. 1(a), which includes a first spacer 131 and a second spacer 132.
Next, referring to FIG. 1(b), in order to achieve an electrical connection to the metal gate or remove the poly-silicon dummy gate so as to fill the metal gate to substitute for the poly-silicon dummy gate, the hard mask 16 on the gate 11 have to be etched back so as to expose the gate 11. However, the hard mask 16 and the shallow trench isolation 109 usually have an identical material, for example, silicon oxide. During etching back the hard mask 16 by a wet etching process, a top portion of the shallow trench isolation 109 is simultaneously etched to form a recess 108. The formation of the recess 108 has disadvantages as follows. The recess 108 causes a thickness of the shallow trench isolation 109 is reduced, thereby increasing a current leakage. In addition, in the subsequent step of forming a contact etch stop layer (CESL) (not shown), the recess 108 will cause to form a seam between the contact etch stop layer and the shallow trench isolation 109.
Therefore, what is needed is a removing method of a hard mask to overcome the above disadvantages.